Design of Self-Timed Circuits Using GaAs MESFETs

This paper presents a method to implement hazardfree functional blocks for self-timed GaAs MESFET-based circuits. The association of the GaAs technology, offering better electrical performance, higher radiation hardness and wider operating temperature range than Silicon one, with the asynchronous digital design, which avoids the generation and routing of global clock signals and consequently the clock skew problems, emerges as an appealing option to build VLSI systems. This approach uses direct-coupled FET logic (DCFL) family to implement Boolean equations in sum-of-sums form, resulting in a simple and fast way to construct such self-timed GaAs circuits. To describe and validate this method, a 16x16bit radix-2 redundant divider has been implemented in 0.6 μm GaAs technology.